xc-SDDIB
Basic PAL/NTSC Video Deinterlacer IP Core

This low-cost deinterlacing IP core converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 progressive format, which can be used either for display or further processing such as H.264 video compression. The core uses a spatial predictor and complex two-dimensional filter to optimally compute pixels on missing lines on a pixel by pixel basis. This combined approach produces the highest possible quality for non motion-adpative deinterlacing.
 
The core accepts either a BT.656 encoded stream or a discrete 8/16 bit stream with hardware vertical and horizontal sync. Industry standard input specifications are either 720/576i @25fps for PAL or 720/525i @29.997 fps for NTSC. Output frame rates are twice the input rate: 50fps for PAL and 60fps for NTSC. In addition, the core can truncate the input both horizontally and vertically thus directly supporting D1, 4CIF and VGA standards.
 
The core's design is fully synchronous allowing for easy integration with other chip components. The input video is isolated from the core using an input FIFO allowing for different input pixel rates while maintaining a constant output pixel rate.
 

The core's input-output latency is only two video lines (130 usec) making it suitable for very time-critical applications.
 
Deliverables include either an FPGA netlist or source RTL, an executable bit-accurate model, a comprehensive testbench and documentation.
 

For more information aoout this core contact us at:
email: info@xicore-ip.com or fill out our contact form:  Contact Form

  • Deinterlaces standard 4:2:2 interlaced video streams into 4:2:0 raster streams.
  • Spatial predictor and two-dimensional interpolation filter produces very high image quality.
  • Directly connects to 8-bit, 4:2:2 interlaced video source
  • Video format support includes either BT.656 or raw input with HSYNC,VSYNC timing.
  • Extremely low input-output latency of two video lines.
  • Variable output frame rate starting with twice the input field rate (50 fps)
  • Configurable input truncator supports D1, 4CIF and VGA sizes.
  • Very low core frequency equal to the output pixel rate (typically 27Mhz).
  • No need for external memory
  • Fully synchronous, pipelined design
  • Bit-accurate executable model
  • Comprehensive testbench and documentation
  • Reference designs available
  • Video compression encoders
  • Surveillance
  • LCD Displays, DVD Players, Digital Video Cameras
  • Set-top Boxes
  • Portable Media Devices

The core's modules are shown in the block diagram and described below.

Reset and Autosync

When asserted this signal holds the entire core in a reset state. When released the core is still held in reset while the input stage is released from reset and waits for the next vertical sync at which time the core is released from reset. This auto-sync function is part of the Xicore core.

Clock Domains

Input Video Clock

This is an input from the external video source used to clock input video, typically from an video decoder chip.

Core and Output Video Clock

The core clock is an input and is used by most of the core's logic. It is the same as the output pixel clock and is twice the input pixel rate.

Video Input

Accepts 4:2:2 formatted video in a BT.656 or a raw stream with hardware vertical and horizontal sync. For raw streams the core supports 8 or 16 bit inputs allowing for glueless connection to a wide variety of video decoder chips. The input clock is defined by the source, typically a video decoder chip, and is independent of the core logic clock. BT.656 formatted streams are decoded and hardware timing signals extracted for the core logic.

Input FIFO

A small FIFO is used at the input to isolated the input video stream from the core logic. This allows the input to support a large number of possible sources whose frequency varies according to the configuraiton. For example, a 16-bit input would feed pixels at 13.5 Mhz while a BT.656 input would be fed at 27Mhz. In either case the core frequency remains fixed at the output pixel rate. The FIFO output is run with the core clock.

Input Video Engine

The input video engine performs two important functions: 1) image sizing and 2) video synchronization. The image sizer consists a simple truncater in both the horizontal and vertical directions. Hence, the core can directly support D1, 4CIF and VGA from a typical PAL/NTSC source.

Video synchronization is an often overlooked but vital function that is included in the core. After power up the video decoder chip starts to feed data to the core. The core is held in reset until configured and enabled by external logic. Once enabled, however, the core will typically start to receive video in the middle of a field, which causes a shift in the video output. After the core has been enabled the its synchronization logic waits until the next vertical sync before releasing the main logic. In this way the processors get the first pixel of the first row of the next field.

Line Buffers

The line buffers store lines of video to perform its work and store output lines for the output processor

Spatial Predictor

Simple interpolation, based only on the values of neighboring pixels limits image quality. Xicore's algorithm uses a spatial predictor to determine the tendency of the pixel as a function of the neighboring pixels and this is used to dynamically alter the interpolation filter to produce an optimal pixel.

Interpolation Filter

Following spatial prediction the interpolation filter is used to compute the actual pixel value using a complex two-dimensional filter resulting in the highest possible image quality.

Output Processor

This module is responsible for outputting the deinterlaced video to the external interface.As it takes two full video lines to perform a deinterlacing function the output processor does not begin to output pixels until the end of the second output line, which corresponds to the end of the first input video line.

The output interface consists of separate pathways for luma (Y) and color (Cb, Cr), each having a separate valid signa. This is necessary since the 4:2:0 video format does not provide valid data on every clock cycle. The output clock is the same as the core clock.

The deinterlacing function converts fields into frames. Hence, the output frame rate is the same as the input field rate, which is 50fps for PAL and 60fps for NTSC. The output frame rate, however, is configurable.

Configuration

The core can be configured using dedicated input signals as follows:

Input Size

Two lines define one of D1, 4CIF or VGA. The raw input video is D1 and the core performs simple truncation to achieve the other size.

Output Frame Rate

Two lines defie one of four possible frame rates: Full (50/60fps), Half, Quarter or Eighth.

 

The core is warranted against defects for one year from date of purchase. Ninety days of phone and email technical support are included. Additional maintenance and support options are available.

 

A comprehensive testbench is included in the core package and includes the following items:

  • Bit Accurate Windows utility emulating the core's algorithm.
  • Xicore IP simulation library
  • Testbench source
  • Video decoder chip simulation model
  • Self verifying testbench operation

The Xicore testbench uses a BFM approach to verification by producing and checking actual video transactions instead of simple vector comparison. A video-decoer chip simulation model opens a interlaced video file -- the same as used by the bit-accurate C model -- and feeds interlaced video to the Xicore deinterlacer simulation model. The deinterlaced output stream is then compared to the stream produced by the bit-accurate utility. In addition, output files are saved for offline analysis.

The Bit-Accurate C model is a Windows/Linux utility that accepts interlaced video files and produces deinterlaced, progressive 4:2:0 output according the Xicore algorithm that can be played on any standard YUV player. It is bit-accurate to the RTL implementation and its output is used by the testbench to verify its operation.

  • Core netlist or RTL source code
  • Synthesis constraints
  • Comprehensive testbench with input video test file library, regression test scripts
  • Windows/Linux bit-accurate model
  • Developer's guide, specifications and system integration guide
  • Complete reference design (optional)