This core bridges between the Xicore family of deinterlacer cores and the Oceanlogic H.264 video encoder. The deinterlacer 4:2:0 luma and chroma video streams are rasterized into line buffers and macroblocks are extracted from the line buffers and fed into the Oceanlogic H.264 encoder.
Connection is completely glueless and complete without any need for any other logic element.
The core is suited for FPGA or ASIC implementation and comes with a testbench and simulation models.
The input is a 4:2:0 video source consisting of vertical/horizontal sync and separate data paths for luma and chroma qualified by respective valid signals. As pixels become available they are written to the internal line buffers which effectively rasterizes the video.
When sixteen lines of luma have completed a READY signal is relayed to the Macroblock Processor which then asserts the READY signal to indicate that a new set of macroblocks are ready for extraction. The processor then waits for a request from the interface on the ld_blk signal. When it arrives the processor then outputs a sequence of 16x16 luma and 8x8 chroma macroblocks for an entire video line width.
As one set of macroblocks are fed to the interface another 16 lines of video are written to the second set of video line buffers. The buffers operate in this ping-pong fashion always assuring that macroblocks will be available as soon as they are ready.
This core has been fully verified using both simulation testbenches and a Oceanlogic H.264 based system.